Displaying items by tag: LEON (processor)

Designed for advanced nano-satellite constellations in LEO and deep space exploration missions the readily available Sirius OBC with LEON3FT delivers ‘always-on’ reliable operations that work every time on time with precision performance. With enhanced error detection and correction, the Sirius OBC is tolerant to Single-Event-Effects (SEE) in logic and data storage. Fault tolerance is secured through TMR (Triple-Modular Redundancy) on all FPGA flip-flops and through boot flash and EDAC (error detection and correction) on memories. The development kit is powered through a mains 12V adaptor, eliminating the need for specialised power supplies or other laboratory equipment.

Sirius spacecraft avionics are modular in design. Modules can be combined to offer redundant configurations, or to simply accommodate mission specific requirements. The Sirius TCM LEON3FT has a standard single string system that consists of an on-board computer (Sirius OBC) and a combined mass memory with CCSDS stack (Sirius TCM). The OBC runs mission specific software and manage the spacecraft system. The TCM receives and stores payload data and platform housekeeping data while at the same time distributing telecommands and serving mass memory data to the transceiver.

Flight proven across multiple mission applications for a range of customer requirements, this readily available solution has a reputation for reliability and performance for advanced small and nano-satellite missions. The Sirius TCM LEON3FT has inherited advanced error detection and correction in it’s design. The real-time operating system runs on a LEON3FT fault-tolerant soft processor, compliant to IEEE 1754 SPARC v8, and fault tolerance is secured by using triple-modular redundancy on FPGA and memory scrubbing.

Sirius spacecraft avionics are modular in design. Modules can be combined to offer redundant configurations or to simply accommodate mission specific requirements. The Sirius TCM LEON3FT has a standard single string system that consists of an on-board computer (Sirius OBC) and a combined mass memory with CCSDS stack (Sirius TCM). The OBC runs mission specific software and manage the spacecraft system. The TCM receives and stores payload data and platform housekeeping data, while at the same time distributing telecommands and serving mass memory data to the transceiver.

Designed for advanced nano-satellite constellations in LEO and deep space exploration missions the readily available Sirius OBC with LEON3FT delivers ‘alwayson reliable operations that work every time on time with precision performance. With enhanced error detection and correction, the Sirius OBC is tolerant to Single-Event-Effects (SEE) in logic and data storage. Fault tolerance is secured through TMR (Triple-Modular Redundancy) on all FPGA flip-flops and through boot flash and EDAC (error detection and correction) on memories.

Sirius spacecraft avionics are modular in design, modules can be combined to offer redundant configurations or to simply accommodate mission specific requirements. The Sirius TCM LEON3FT has a standard single string system that consists of an on-board computer (Sirius OBC) and a combined mass memory with CCSDS stack (Sirius TCM). The OBC runs mission specific software and manage the spacecraft system. The TCM receives and stores payload data and platform housekeeping data while at the same time distributing telecommands and serving mass memory data to the transceiver.

Aeroflex Gaisler (ex Gaisler Research) is a Swedish company providing complete framework for the development of processor-based 'System-on-a-Chip' designs.

The key product is the LEON synthesizable processor model together with a full development environment and a library of IP cores (GRLIB). Our personnel have extended design experience, and have been involved in establishing European standards for ASIC and FPGA development. Aeroflex Gaisler has a long experience in the management of ASIC development projects, and in the design of flight quality microelectronic devices. The company specializes in digital hardware design (ASIC/FPGA) for both commercial and aerospace applications. We offer services and products in the following fields:

LEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set.

It was originally designed by the European Space Research and Technology Centre (ESTEC), part of the European Space Agency (ESA), and after that by Gaisler Research (now Aeroflex Gaisler). It is described in synthesizable VHDL.

LEON has a dual license model: A LGPL/GPL FLOSS license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product. The core is configurable through VHDL generics, and is used in system-on-a-chip (SOC) designs both in research and commercial settings.

ESA's Alphasat telecom satellite, the Proba-V microsatellite, the Earth-monitoring Sentinel family and the BepiColombo mission to Mercury are among the missions to use an advanced 32-bit microprocessor – engineered and built in Europe.

All of them incorporate the LEON2-FT chip, commercially known as the AT697. Engineered to operate within spacecraft computers, this microprocessor is manufactured by Atmel in France but originally designed by ESA.